1. Field of the Invention
The present invention relates to a semiconductor device, and in particular to a semiconductor integrated circuit which achieves a circuit structure allowing fast operation of an ECL (Emitter Controller Logic) integrated circuit without increasing a current consumption.
2. Description of the Background Art
FIG. 12 is a circuit diagram showing a concept of an ECL active-pull-down circuit disclosed in "A 23-ps/2.1-mWECL gate with an ac-coupled active-pull-down emitter-follower stage" in IEEE J. Solid-State Circuits, Vol. SC-24, No. 5, October 1989, pp. 1301-1306. Referring to FIG. 12, an ECL active-pull-down circuit includes a switching stage circuit 31 which is connected to a VCC supply terminal 1 and a VEE supply terminal 2, receives an input signal A and a reference potential VBB and outputs a first signal B and a second signal C, i.e., a complementary signal of first signal B, an emitter-follower transistor 60 which receives first signal B on its base and is arranged between VCC supply terminal 1 and output node 20, a bias circuit 32 which receives second signal C via a control capacitor 72 and is connected to VCC supply terminal 1 and VEE supply terminal 2, and a pull-down transistor 61 which receives on its base an output signal from bias circuit 32, has a collector connected to an output terminal node 20 and has an emitter connected to VEE supply terminal 2. Switching stage circuit 31 includes an npn bipolar transistor 50 which receives input signal A on its base via an input terminal 3, and has a collector connected to a node 15 and an emitter connected to a node 56, a bipolar transistor 51 which receives VBB potential, i.e., reference potential having an intermediate potential of a logical amplitude via a VBB terminal 4, and has a collector connected to a node 16 and an emitter connected to a node 56, and an npn bipolar transistor 52 which receives on its base a VCS potential via a VCS terminal 5, and has a collector connected to a node 56 and an emitter connected to second power supply 2 via an emitter resistance. Resistances 53 and 54 for generating predetermined potentials are arranged between VCC supply terminal 1 and nodes 15 and 16, respectively. npn transistor 52 and resistance 55 serve as a constant current supply for switching stage circuit
Bias circuit 32 includes a resistance 74 connected between VCC supply terminal 1 and a node 13, diode 75 and a resistance 73 connected between node 13 and VEE supply terminal 2. Second control signal C is supplied to node 13 via control capacitor 72. First signal B, i.e., an output of switching stage circuit 31 is supplied to the base of emitter-follower transistor 60, and an output signal D is taken out from its emitter via an output node 20.
Referring to FIG. 13, operation of the ECL active-pull-down circuit shown in FIG. 12 will be described below. When input signal A sent to input terminal 3 is "L" (-1.6 V), node 15 is "H" (0 V) and emitter-follower transistor 60 is turned on, so that output signal D, i.e., the potential of output terminal 20 is "H" (-0.8 V). In this state, the potential of reference potential VBB is -1.2 V, the potential of VCC is 0 V and the potential of VEE is -5.2 V.
Pull-down transistor 61 is supplied on its base with an intended potential determined by bias circuit 32, and flows an intended emitter current of an npn bipolar transistor. When input signal A changes to "H" (-0.8 V), first signal B changes to "L" (1.6 V), and output signal D starts to change to "L" (-1.6 V) (see A and B in FIG. 13). At this time, second control signal C sent from switching stage circuit 31 serves to increase the potential of node 13 via the coupling with control capacitor 72. This results in increase of the current which pulls down a collector current 61cI of pull-down transistor 61, i.e., output signal D, and thus output signal D can be raised rapidly. When a certain time elapses, the potential of node 13 is restored to an initial value and thus keeps the potential of output signal D at the potential of "L", so that a stationary emitter-follower current is suppressed.
Conversely, when input signal A changes from "H" (-0.8 V) to "L" (-1.6 V), the potential of node 13 is kept at a low potential for a short time, so that a current flowing from output terminal node 20 to VEE supply terminal decreases, and thus output signal D can be raised rapidly.
FIG. 14 shows a structure of the conventional ECL active-pull-down circuit in which outputs are produced in a differential manner. Referring to FIG. 14, this structure requires bias circuits 32a and 32b as well as control capacitors 72a and 72b for differential output signals D1 and D2, respectively.
The conventional ECL active-pull-down circuit has the structure described above. In this structure, bias circuit 32 for driving pull-down transistor 61 must flow a stationary current. Moreover, if there are provided a plurality of output terminals, bias circuits 32 equal in number to the terminals are required as described with reference to FIG. 14. Therefore, it has been desired to reduce or eliminate the bias current from the viewpoint of low power consumption. As the capacitance of control capacitor 72 increases, the drive effect of pull-down transistor 61 increases. Therefore, it is desired to use the control capacitor of a relatively large capacitance of several microfarads. The control capacitor of the large capacitance increases a layout occupied area. Further, if the outputs are produced in a differential manner, the control capacitor must be provided for each output, which also increases the layout occupied area.